Michiko Inoue und Hideo Fujiwara - Info zur Person

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IEICE Trans - Delay Fault Testing of Processor Cores in Functional...

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Delay Fault Testing of Processor Cores in Functional Mode. Virendra SINGH Michiko INOUE Kewal K. SALUJA Hideo FUJIWARA. Publication ...

IEICE Trans

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IEICE TRANSACTIONS on Information and Systems. Archive ... Distributed Shared Memory. Sen MORIYA Katsuro SUDA Michiko INOUE Toshimitsu MASUZAWA Hideo FUJIWARA ...

Graph Drawing: 6th International Symposium, GD '98 Montreal, Canada,...

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183 Kunihiko Hayashi, Michiko Inoue, Toshimitsu Masuzawa, and Hideo Fujiwara Drawing Algorithms for Series-Parallel Digraphs in Two and Three ...

dblp: Hideo Fujiwara

dblp.uni-trier.de

List of computer science publications by Hideo Fujiwara

Search results for "separable primary inputs" – FacetedDBLP

dblp.l3s.uni-hannover.de

Michiko Inoue, Emil Gizdarski, Hideo Fujiwara: A class of sequential circuits with combinational test generation complexity under single-fault assumption.

Search results for "Hideo Fujiwara" – FacetedDBLP

dblp.l3s.de

IEEE Design & Test of Computer...(3) IEEE Trans. VLSI Syst.(3) DAC(2) DISC(2) More (+10 of total 36). Authors. Hideo Fujiwara(172) Michiko Inoue(33) ...

4. Publications - Hideo Fujiwara - Work

sites.google.com

[ PDF]; Michiko Inoue and Hideo Fujiwara, "VLSI High-Level Synthesis for Testability: A Survey and Perspective," J. REAJ, Vol. 20, No. 5, pp , June ...

CiteSeerX — Abstract Software-Based Delay Fault Testing of Processor...

citeseerx.ist.psu.edu

by Virendra Singh , Michiko Inoue , Kewal K Saluja , Hideo Fujiwara ... author = {Virendra Singh and Michiko Inoue and Kewal K Saluja and Hideo Fujiwara},

ken-system: Design for Testability of Software-Based Self-Test for...

ken.ieice.org

... Nakazato, Satoshi Ohtake, Michiko Inoue, Hideo Fujiwara (NAIST) ... Michiko Inoue. 3rd Author's Affiliation. Nara Institute of Science and Technology (NAIST) ...

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Michiko Inoue und Hideo Fujiwara Person-Info