Shyam Sundar Dhar - Veröffentlichungen allgemein

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Design of a Fault-Tolerant Conditional Sum Adder | SpringerLink

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Fault tolerance is the ability of a system to retain its normal operation without failure when some part of the system fails to operate properly. It increases...

Anindya Sundar Dhar - Metakgp Wiki

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Anindya Sundar Dhar. Anindya Sundar Dhar.jpg. Department, Electronics & Electrical Communication Engineering. Research Area(s). VLSI Architecture Design.

Anindya Sundar Dhar - Metakgp Wikiwiki.metakgp.org › Anindya_Sund...

wiki.metakgp.org

Anindya Sundar Dhar.jpg. Department, Electronics & Electrical Communication Engineering. Research Area(s). VLSI Architecture Design. Year Joined,

Prediction of Epitope-Based Peptides for Vaccine Development from...

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Richa Jain1. • Shyam Dhar Dubey2. • Sharad Bhatnagar2. •. Nabeel Ahmad2. Accepted: 24 August Published online: 4 September © Springer ...

Pipelined VLSI Architecture using CORDIC for Transform Domain...

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In this paper, a pipelined architecture using CORDIC for realization of transform domain equalizer is presented. Transform domain equalizer has much faster

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Veröffentlichungen allgemein Shyam Sundar Dhar

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Design of a Fault-Tolerant Conditional Sum Adder | SpringerLink

Anindya Sundar Dhar - Metakgp Wiki

Anindya Sundar Dhar - Metakgp Wikiwiki.metakgp.org › Anindya_Sund...

Prediction of Epitope-Based Peptides for Vaccine Development from...

Pipelined VLSI Architecture using CORDIC for Transform Domain...